Hardware Architectural Specification – a design-level view of the NVDLA hardware architecture, including detail on each sub-component, and register-level documentation.
This is the non-configurable “full-precision” version of NVDLA. The design code is in nvdlav1 branch.
In-memory data formats – description of the in-memory format for weight and activation data.
Integrator’s Manual – a guide for SoC integrators, including a walk-through of the NVDLA build infrastructure, NVDLA’s testbenches, and synthesis scripts.
Precision Preservation – the technologies used to keep the precision when formats INT8/INT16/FP16 are used.
LUT programming – the guide to programming lut tables
Unit Description – description of internal architecture of sub-units
Programming Guide – programming guide of sub-units
This version is scalable design of NVDLA. Currently, the config nv_small is verified. The architecture of sub-units is same as NVDLA v1.
NVDLA Environment Setup Guide – Please follow this document to setup tools and dependency libraries
Scalability parameters and ConfigROM – Scalability parameters and ConfigROM contents in nv_large and nv_small configurations
Integrator’s Manual – a guide for SoC integrators, including NVDLA system inferce introduction, synthesis scripts.
NVDLA Verification Suite User Guide – NVDLA Verification Suite User Guide